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The course focuses on learning advanced digital design to Verilog HDL and various DFT concepts, scan chain insertion, fault simulation, fault collapsing, and structured techniques, etc.. The course also focuses on providing an exposure to Tessent Shell, which is an interface to Tessent tools through a demo on the Scan-chain insertion technique.
Offered by Maven Silicon15 hrs theory · 30 hrs practicalEnglishMaven Silicon Experts
The course focuses on learning advanced digital design to Verilog HDL and various DFT concepts, scan chain insertion, fault simulation, fault collapsing, and structured techniques, etc.. The course also focuses on providing an exposure to Tessent Shell, which is an interface to Tessent tools through a demo on the Scan-chain insertion technique.
ASIC Design Engineer, Design Engineer, FPGA Design Engineer, SoC Design Engineer, RTL Design Engineer, DFT Engineer, DFT Verification Engineer, DFT Architect, VLSI Design Engineer
Certification
