Engineering Credit eligibleNCrF 7.0

VLSI Verification - Campus Connect

Name: VLSI Verification - Campus Connect
Price: 2999 INR

This course aims to provide a comprehensive journey into mastering verification methodologies in VLSI design by covering a range of modules, from RTL design to Verification concepts. It introduces the basics and then discusses in depth SystemVerilog language concepts, memories, interfaces, object-oriented programming, randomization, functional coverage, and more. The course offers an overview of the Universal Verification Methodology.

₹2,999

Offered by Maven Silicon15 hrs theory · 30 hrs practicalEnglishMaven Silicon Experts

Learning outcomes

To learn digital design, VLSI principles, and advanced techniques for efficient RTL design

To enable hands-on experience in digital design using Verilog HDL

To explore various effective verification methodologies to verify VLSI designs efficiently

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Intended audience

ASIC Design Engineer, Design Engineer, FPGA Design Engineer, SoC Design Engineer, RTL Design Engineer, Verification Engineer, ASIC Verification Engineer, SoC Verification Engineer, Design Verification Engineer, VLSI Verification Engineer

Prerequisites

Prior knowledge in Digital electronics and Verilog HDL, Competency level - Intermediate

Level

Certification

Skills you'll gain

Basics of VLSI TechnologySoC Design KnowledgeSoC Architecture UnderstandingVLSI Design FlowRTL codingSimulationand synthesis tools usageSystem architecture understandingImplementing Logic functions - registersmemoriesarithmetic operationsetc.Simulation and synthesis tools usageDifferent abstraction levelsVerification Methodology ExpertiseVerification Process KnowledgeReusable testbench developmentVerification Environment ArchitectureConstraint Random Coverage Driven Verification ( CRCDV)Analytical and problem-solving skills

VLSI Verification - Campus Connect

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VLSI Verification - Campus Connect

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Skills you'll gain

The future belongs
to those who keep learning.